`timescale 1ns/1ps

module tb_add();

reg [7:0] a;
reg [7:0] b;
wire [15:0] c;

add#(.len(8) ) u_add(
    .a(a),
    .b(b),
    .c(c)
);

initial begin
    a <= 8'd2;
    b <= 8'd1;
    #100
    a <= 8'h10;
    b <= 8'ha;
end

endmodule